1. Field of the Invention
The present invention disclosed herein relates to analog-to-digital conversion circuits. More particularly, but not by way of limitation, the invention disclosed herein is concerned with a correlated double-sampling and amplifying circuit for a CMOS image sensor, and a cyclic analog-to-digital converter including such a circuit.
2. Description of the Related Art
A general complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) has an active pixel sensor (APS) array that includes multiple pixels arranged in rows and columns. An analog-to-digital converter (ADC) processes received pixel data, for example data associated with all columns in a selected row of the APS array.
Such an ADC typically includes a correlated double sampling (CDS) circuit. In a CDS operation, an output node is reset to a predetermined reference value, a pixel charge (signal value) is transferred to the output node, and the final value of charge assigned to the pixel is the difference between the reset and signal values. The CDS circuit may also amplify the received reset and signal values, for instance by a factor of two.
A conventional CDS circuit includes multiple capacitors for sampling and amplifying the reset and signal voltages, and a differential amplifier for outputting a difference between the amplified voltages. Three capacitors are typically coupled to each of the inverted and non-inverted input terminals of the differential amplifier. Therefore, in total, the conventional CDS circuit of the ADC includes six capacitors for the CDS operation and amplification of the input signal.
Such circuits are disadvantageous in that the six capacitors occupy a substantial portion of layout area of the CDS circuit, increasing a chip area of the CMOS image sensor. What is needed is a CDS circuit that is more space efficient.